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Embedded System Tools Guide (EDK 6.2i) www.xilinx.com 269
UG111 (v1.4) January 30, 2004 1-800-255-7778
Design Considerations
R
PORT <nPLB>_MRearbitrate = PLB_MRearbitrate, DIR=I, BUS=MPLB
PORT <nPLB>_MWrBTerm = PLB_MWrBTerm, DIR=I, BUS=MPLB
PORT <nPLB>_MWrDAck = PLB_MWrDAck, DIR=I, BUS=MPLB
PORT <nPLB>_MSSize = PLB_MSSize, DIR=I, VEC=[0:1], BUS=MPLB
Slave PLB Ports
For interconnection to the PLB, all slaves must provide the following connections:
PORT <Sln>_addrAck = Sl_addrAck, DIR=O, BUS=SPLB
PORT
<Sln>_MErr = Sl_MErr, DIR=O, VEC=[0:C_NUM_MASTERS-1], BUS=SPLB
PORT
<Sln>_MBusy = Sl_MBusy, DIR=O, VEC=[0:C_NUM_MASTERS-1], BUS=SPLB
PORT
<Sln>_rdBTerm = Sl_rdBTerm, DIR=O, BUS=SPLB
PORT
<Sln>_rdComp = Sl_rdComp, DIR=O, BUS=SPLB
PORT
<Sln>_rdDAck = Sl_rdDAck, DIR=O, BUS=SPLB
PORT
<Sln>_rdDBus = Sl_rdDBus, DIR=O, VEC=[0:C_PLB_DWIDTH-1],BUS=SPLB
PORT
<Sln>_rdWdAddr = Sl_rdWdAddr, DIR=O, VEC=[0:3], BUS=SPLB
PORT
<Sln>_rearbitrate = Sl_rearbitrate, DIR=O, BUS=SPLB
PORT
<Sln>_SSize = Sl_SSize, DIR=O, VEC=[0:1], BUS=SPLB
PORT
<Sln>_wait = Sl_wait, DIR=O, BUS=SPLB
PORT
<Sln>_wrBTerm = Sl_wrBTerm, DIR=O, BUS=SPLB
PORT
<Sln>_wrComp = Sl_wrComp, DIR=O, BUS=SPLB
PORT
<Sln>_wrDAck = Sl_wrDAck, DIR=O, BUS=SPLB
PORT <nPLB>_ABus = PLB_ABus, DIR=I, VEC=[0:C_PLB_AWIDTH-1], BUS=SPLB
PORT <nPLB>_BE = PLB_BE, DIR=I, VEC=[0:(C_PLB_DWIDTH/8)-1], BUS=SPLB
PORT <nPLB>_PAValid = PLB_PAValid, DIR=I, BUS=SPLB
PORT <nPLB>_RNW = PLB_RNW, DIR=I, BUS=SPLB
PORT <nPLB>_abort = PLB_abort, DIR=I, BUS=SPLB
PORT <nPLB>_busLock = PLB_busLock, DIR=I, BUS=SPLB
PORT <nPLB>_compress = PLB_compress, DIR=I, BUS=SPLB
PORT <nPLB>_guarded = PLB_guarded, DIR=I, BUS=SPLB
PORT <nPLB>_lockErr = PLB_lockErr, DIR=I, BUS=SPLB
PORT <nPLB>_masterID = PLB_masterID, DIR=I,VEC=[0:C_PLB_MID_WIDTH-1],
BUS=SPLB
PORT <nPLB>_MSize = PLB_MSize, DIR=I, VEC=[0:1], BUS=SPLB
PORT <nPLB>_ordered = PLB_ordered, DIR=I, BUS=SPLB
PORT <nPLB>_pendPri = PLB_pendPri, DIR=I, VEC=[0:1], BUS=SPLB
PORT <nPLB>_pendReq = PLB_pendReq, DIR=I, BUS=SPLB
PORT <nPLB>_reqPri = PLB_reqPri, DIR=I, VEC=[0:1], BUS=SPLB
PORT <nPLB>_size = PLB_size, DIR=I, VEC=[0:3], BUS=SPLB
PORT <nPLB>_type = PLB_type, DIR=I, VEC=[0:2], BUS=SPLB
PORT <nPLB>_rdPrim = PLB_rdPrim, DIR=I, BUS=SPLB
PORT <nPLB>_SAValid = PLB_SAValid, DIR=I, BUS=SPLB
PORT <nPLB>_wrPrim = PLB_wrPrim, DIR=I, BUS=SPLB
PORT <nPLB>_wrBurst = PLB_wrBurst, DIR=I, BUS=SPLB
PORT <nPLB>_wrDBus = PLB_wrDBus, DIR=I, VEC=[0:C_PLB_DWIDTH-1],BUS=SPLB
PORT <nPLB>_rdBurst = PLB_rdBurst, DIR=I, BUS=SPLB
Design Considerations
This section includes design considerations.
Unconnected Ports
Unconnected output ports are assigned open, and unconnected input ports are either set to
GND or VCC.
- Embedded System 1
- Tools Guide 1
- 1-800-255-7778 2
- Embedded System Tools Guide 3
- UG111 (v1.4) January 30, 2004 3
- About This Guide 5
- Additional Resources 6
- Typographical 7
- Online Document 8
- Table of Contents 9
- Chapter 7: Library Generator 13
- Chapter 12: GNU Debugger 18
- Chapter 1 27
- Tool Flows 28
- Software Platform Creation 29
- Figure 1-4: Software Platform 30
- Some Useful Tools 31
- Software Debugging 32
- Verifying Tools Setup 34
- Xilinx Platform Studio (XPS) 35
- Tools Supported 36
- Project Management 37
- Opening An Existing Project 38
- Getting Help 38
- XPS Interface 39
- System Tab 40
- Applications Tab 40
- Transcript Window (Output) 40
- Platform Management 41
- Library and O/S Parameters 42
- Adding Files 42
- Deleting Files from Project 42
- Editing Files 43
- Xmdstub Software Applications 43
- Environment 44
- Optimization 44
- Directories 44
- Advanced 44
- Project Options 45
- Device and Repository 46
- Hierarchy and Flow 46
- HDL and Simulation 47
- Debug and Simulation 49
- PBD Editor 49
- PBD Editor Workspace 50
- System Tabs 51
- Naming an Instance 52
- Setting Symbol Properties 53
- Connecting Ports 54
- Editing the Block Diagram 56
- Viewing Object Information 57
- Zooming in the Workspace 57
- XPS “No Window” Mode 58
- Available Commands 59
- Creating A New Empty Project 59
- Reading MSS File 60
- Saving Files and Project 60
- Setting Project Options 60
- Executing Flow Commands 61
- Adding a Software Application 62
- Option Name Description 63
- Closing A Project and Exiting 64
- Limitations And Workarounds 64
- Base System Builder 65
- Selecting A Processor 67
- BSB Flow 69
- Adding Internal Peripherals 70
- Configuring Software Settings 71
- Exiting BSB 74
- Chapter 4 77
- Creating New Peripherals 79
- Select Bus Interface 80
- Select IPIF Services 80
- Table 4-3: IPIF Services 81
- IPIF Feature Description 81
- Configure FIFOs 82
- Configure Interrupt Handling 82
- Configure Address Ranges 84
- Configure the IPIC 85
- Select Source File Types 88
- HDL Source Files 88
- HDL Analysis Information 89
- Bus Interfaces 91
- Netlist files 95
- Documentation files 96
- Finishing Peripheral Import 96
- Directory or file Description 97
- Platform Generator 99
- Tool Options 100
- <Library Name> 101
- -lp <library_path> 101
- About Memory Generation 102
- BMM Policy 103
- Reserved MHS Parameters 104
- Current Limitations 105
- Synthesis Netlist Cache 105
- Chapter 5: Platform Generator 106
- Simulation Model Generator 107
- Simulation Basics 108
- Simulation Libraries 108
- EDK Library 109
- Simulation Models 110
- Behavioral Models 111
- Structural Models 111
- SimGen Syntax 112
- Output Files 114
- Memory Initialization 115
- Simulating Your Design 115
- Library Generator 117
- -xmdstub proc_inst_name 119
- -executable proc_inst_name 119
- Load Path 120
- MDD/MLD and Tcl 123
- MSS Parameters 124
- Libraries 124
- STDIN and STDOUT Peripherals 126
- Chapter 8 127
- Signal Naming Conventions 129
- Invoking PsfUtility 129
- Non-Exclusive Bus Interfaces 130
- Exclusive Bus Interfaces 130
- BRAM PORTS 130
- Global IP Core Options 131
- Properties on Ports 132
- DRC Checks in PsfUtility 133
- Verilog Language Support 134
- VHDL Peripheral Definitions 134
- Reserved Parameters 136
- Global Ports 139
- Slave DCR Ports 139
- Slave LMB Ports 140
- Master OPB Ports 141
- Slave OPB Ports 142
- Master/Slave OPB Ports 143
- Master PLB Ports 144
- Slave PLB Ports 145
- PLB Slave Outputs 146
- PLB Slave Inputs 146
- "M:OPB_SLAVE"; 149
- "ACTIVE"; 151
- "VHDL"; 151
- "PERIPHERAL"; 152
- "LOGICORE"; 152
- "my_lic_val"; 153
- "TRUE"; 153
- "BRAM_CNTLR"; 153
- MIN_SIZE Attribute 154
- ADDRESS and PAIR Attribute 155
- XRANGE Attribute 155
- THREE_STATE Attribute 156
- IOB_STATE Attribute 157
- SIGIS Attribute 157
- INITIALVAL Attribute 158
- BUSIF Attribute 158
- SIGVAL Attribute 158
- Format Revision Tool 159
- Revup from EDK 3.2 to EDK 6.1 160
- Bitstream Initializer 161
- GNU Compiler Tools 163
- GNU Compiler Framework 164
- Please note that the 165
- Compiler Options 166
- Compiler Usage and Options 167
- -l libraryname 168
- -L Lib Directory 168
- -I Directory Name 168
- Linker Options 169
- Linker Scripts 169
- Search Paths 169
- File Extensions 170
- Compiler Interface 171
- MicroBlaze GNU Compiler 172
- MicroBlaze Assembler 174
- MicroBlaze Linker 175
- Initialization Files 176
- Command Line Arguments 177
- Interrupt Handlers 177
- PowerPC GNU Compiler 178
- GNU Debugger 179
- Tool Usage 180
- MicroBlaze GDB Targets 181
- GDB Built-in Simulator 182
- PowerPC Targets 183
- GDB Command Reference 184
- Chapter 13 185
- XMD Usage 186
- PowerPC Target 188
- JTAG chain options 189
- PPC405 options 189
- PowerPC Target Requirements 190
- PowerPC 405 191
- PowerPC Simulator Target 195
- Cycle_Accurate 196
- MicroBlaze MDM Target 197
- MDM Target options 198
- JTAG cable options 198
- MicroBlaze options 199
- MDM Target requirements 199
- JTAG-based UART in MDM 204
- MicroBlaze Stub Target 208
- Serial Port options 209
- Local Memory 210
- MicroBlaze Simulator Target 211
- XMD Internal Tcl Commands 212
- Chapter 14 215
- File and IP Naming Rules 216
- Is Your IP Pure HDL? 218
- Chapter 15 219
- Comments 220
- MHS Example 220
- MHS Syntax 221
- Bus Interface 222
- Global Parameter 223
- Local Parameter 224
- Local Bus Interface 224
- Global Port 225
- SENSITIVITY 226
- Local Port 227
- Design Considerations 227
- Unconnected Ports 228
- Constant Assignments 228
- Concatenation 228
- Internal vs. External Signals 229
- External Interrupt Signals 229
- Chapter 16 231
- MPD Example 232
- Bus Interface Keywords 234
- EXCLUDE_BUSIF 235
- SHARES_ADDR 235
- IO Interface 236
- Option Keywords 237
- ADDR_SLICE 238
- ARCH_SUPPORT 239
- CORE_STATE 239
- IMP_NETLIST 240
- IP_GROUP 240
- IPLEVEL_DRC_PROC 241
- IS_COMPATIBLE_WITH 241
- SYSLEVEL_DRC_PROC 243
- TCL_FILE 243
- USAGE_LEVEL 243
- Parameter 244
- Table 16-11: ADDRESS Values 245
- ADDRESS Definition 245
- ADDR_TYPE 246
- ASSIGNMENT 246
- BITWIDTH 246
- BRIDGE_TO 246
- CACHEABLE 247
- GUI_PERMIT 247
- IPLEVEL_UPDATE_PROC 248
- LONG_DESC 248
- MIN_SIZE 248
- Parameter Naming Conventions 249
- Port Keywords 250
- ASSIGNMENT Definition 252
- INTERRUPT_PRIORITY 253
- IOB_STATE 254
- INITIALVAL 254
- THREE_STATE 255
- Port Naming Conventions 256
- DCR Slave Inputs 257
- LMB Slave Outputs 257
- LMB Slave Inputs 257
- OPB Master Outputs 258
- OPB Master Inputs 258
- OPB Slave Outputs 258
- OPB Slave Inputs 259
- PLB Master Outputs 259
- PLB Master Inputs 260
- Reserved Parameter Names 261
- C_NUM_MASTERS 263
- C_NUM_SLAVES 263
- C_DCR_AWIDTH 263
- C_DCR_DWIDTH 263
- C_DCR_NUM_SLAVES 263
- C_LMB_AWIDTH 264
- C_LMB_DWIDTH 264
- C_LMB_MASK 264
- C_LMB_NUM_SLAVES 264
- C_OPB_AWIDTH 264
- C_OPB_DWIDTH 265
- C_OPB_NUM_MASTERS 265
- C_OPB_NUM_SLAVES 265
- C_PLB_AWIDTH 265
- C_PLB_DWIDTH 265
- Reserved Port Connections 266
- Scalable Data path 270
- Interrupt Signals 270
- 3-state (InOut) Signals 271
- Chapter 17 273
- Black-Box Definition (BBD) 275
- BBD Examples 276
- Chapter 19 277
- Requirements 278
- MSS Example 278
- Global Parameters 279
- Instance Specific Parameters 280
- PROC_INSTANCE Option 281
- HW_INSTANCE Option 281
- OS_NAME Option 281
- OS_VER Option 281
- DRIVER_NAME Option 281
- DRIVER_VER Option 282
- INT_HANDLER Option 282
- LIBRARY_NAME Option 282
- LIBRARY_VER Option 282
- MDD/MLD Specific Parameters 283
- OS Specific Parameters 283
- Processor Specific Parameters 284
- COMPILER_FLAGS Option 285
- EXTRA_COMPILER_FLAGS Option 285
- Chapter 20 287
- MLD Format Specification 288
- Example Tcl File of a library 290
- Example MLD file for an OS 291
- Example Tcl File of an OS 291
- Conventions 292
- OS/Library Definition 292
- Keywords 293
- Chapter 21 297
- MDD Format Specification 298
- MDD file example 299
- Example Tcl File 300
- MDD Parameter Description 301
- Address Management 307
- Special Addresses 308
- OPB Address Range Details 308
- Address Map 308
- Memory Speeds and Latencies 309
- System Address Space 309
- Default User Address Space 310
- Advanced User Address Space 310
- Object-file Sections 311
- UG111_11_111903 312
- Minimal Linker Script 313
- Linker Script 313
- MicroBlaze Processor 315
- PowerPC Processor 316
- Default Linker Options 317
- Interrupt Management 323
- UG111_13_111903 325
- Limitations 326
- External Interrupt Port 327
- PowerPC Interrupt Management 328
- Libgen Customization 329
- Example Systems 330
- Example MHS File Snippet 331
- Example MSS File snippet 331
- Example C Program 331
- Procedure 333
- Example Systems for PowerPC 337
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