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CHAPTER 7: SIMULATION
INTRODUCTION
128 ■ INTRODUCTION TO QUARTUS II ALTERA CORPORATION
Introduction
You can perform functional and timing simulation of your design by using
EDA simulation tools or the Quartus
®
II Simulator.
The Quartus II software provides the following features for performing
simulation of designs in EDA simulation tools:
■ NativeLink
®
integration with EDA simulation tools
■ Generation of output netlist files
■ Functional and timing simulation libraries
■ Generation of test bench template and memory initialization files
■ Generation of Signal Activity Files (.saf)
Figure 1 shows the simulation flow with EDA simulation tools and the
Quartus II Simulator.
Figure 1. Simulation Flow
Quartus II
EDA Netlist Writer
quartus_eda
EDA
Simulation Tool
(Functional)
Functional
simulation
libraries
Quartus II Simulator
quartus_sim
EDA
Simulation Tool
(Timing)
Quartus II
Waveform Editor
Timing simulation
libraries
Verilog Output
Files, VHDL
Output Files &
test bench files
Test bench
files
Verilog Output Files (.vo),
VHDL Output Files (.vho),
Standard Delay Format
Output Files (.sdo) &
test bench files (.vt, .vht)
from Quartus II
Fitter
Waveform files
Signal
Activity
Files (.saf)
- Introduction to 1
- Contents 3
- TABLE OF CONTENTS 4
- Documentation Conventions 9
- Terminology 10
- Design Flow 11
- Introduction 12
- CHAPTER 1: DESIGN FLOW 13
- Quartus II Help 16
- EDA Tool Design Flow 20
- EDA TOOL DESIGN FLOW 21
- HAPTER 1: DESIGN FLOW 22
- OOL DESIGN FLOW 22
- Command-Line Design Flow 26
- Command-Line Executables 27
- OMMAND-LINE DESIGN FLOW 28
- COMMAND-LINE DESIGN FLOW 30
- Using Standard Command-Line 33
- Commands & Scripts 33
- Using Tcl Commands 34
- Creating Makefile Scripts 37
- Planning 40
- Design Entry 43
- Creating a Project 45
- CHAPTER 2: DESIGN ENTRY 46
- CREATING A PROJECT 46
- Using Revisions 47
- Creating a Design 53
- CREATING A DESIGN 54
- Using Altera Megafunctions 57
- Megafunctions 58
- Using the MegaWizard Plug-In 59
- Inferring Megafunctions 61
- USING ALTERA MEGAFUNCTIONS 62
- Instantiation by Inference 63
- Constraint Entry 65
- Using the Assignment Editor 67
- CHAPTER 3: CONSTRAINT ENTRY 68
- USING THE ASSIGNMENT EDITOR 68
- Using the Pin Planner 69
- Using the Settings Dialog Box 70
- USING THE SETTINGS DIALOG BOX 71
- Assigning Design Partitions 72
- Design Partitions Window 73
- Importing Assignments 74
- Verifying Pin Assignments 75
- VERIFYING PIN ASSIGNMENTS 76
- Synthesis 77
- VHDL Integrated Synthesis 79
- CHAPTER 4: SYNTHESIS 80
- HAPTER 4: SYNTHESIS 83
- Attributes 85
- Optimization Options 88
- Place & Route 98
- CHAPTER 5: PLACE & ROUTE 100
- INTRODUCTION 100
- Compilation 101
- Analyzing Fitting Results 102
- ANALYZING FITTING RESULTS 103
- File to View Fitting Results 104
- Analyze Results 105
- Design Reliability 107
- Optimizing the Fit 108
- Setting Fitter Options 109
- OPTIMIZING THE FIT 110
- Back-Annotation 118
- Block-Based Design 121
- CHAPTER 6: BLOCK-BASED DESIGN 123
- Using LogicLock Regions 124
- USING LOGICLOCK REGIONS 125
- Down Incremental Compilation 127
- Assignments 130
- Simulation 134
- The ModelSim-Altera Software 136
- design 136
- Settings 137
- CHAPTER 7: SIMULATION 138
- EDA Simulation Flow 139
- NativeLink Simulation Flow 140
- Manual Timing Simulation Flow 140
- Simulation Libraries 141
- HAPTER 7: SIMULATION 142
- Simulating Designs with the 143
- Quartus II Simulator 143
- Creating Waveform Files 145
- Using the Simulator Tool 146
- Timing Analysis 148
- Quartus II Software 150
- CHAPTER 8: TIMING ANALYSIS 151
- Performing a Timing Analysis 155
- Performing an Early Timing 157
- Estimate 157
- Using the Report Window 159
- Using EDA Tools 164
- Using the PrimeTime Software 166
- Using the Tau Software 167
- Timing Closure 168
- CHAPTER 9: TIMING CLOSURE 170
- Making Assignments 172
- Achieve Timing Closure 174
- Soft LogicLock Regions 177
- Path-Based Assignments 177
- Figure 5. Paths Dialog Box 178
- Power Analysis 180
- PowerPlay Power Analyzer 181
- CHAPTER 10: POWER ANALYSIS 182
- Estimator 185
- HAPTER 10: POWER ANALYSIS 186
- Programming & 187
- Configuration 187
- Converting Programming Files 196
- Debugging 201
- Using the SignalTap II Logic 203
- Analyzer 203
- Logic Analyzer 204
- CHAPTER 12: DEBUGGING 205
- Analyzing SignalTap II Data 209
- Using SignalProbe 211
- USING SIGNALPROBE 212
- Using the In-System Memory 214
- Content Editor 214
- Map Viewer 216
- Using the Chip Editor 217
- Thirteen 218
- Fourteen 227
- PECIFYING ADDITIONAL SETTINGS 231
- System-Level Design 233
- Creating SOPC Designs with 236
- SOPC Builder 236
- Generating the System 237
- DSP Builder 238
- Instantiating Functions 239
- Generating Simulation Files 239
- Generating Synthesis Files 239
- Software Development 241
- MegaWizard Plug-In 245
- Quartus II 245
- Software Builder 245
- ■ Raw Binary Files (.rbf) 246
- ■ SRAM Object Files (.sof) 246
- ■ Tabular Text Files (.ttf) 246
- Seventeen 250
- ■ Mentor Graphics 252
- ■ Altera Quartus II software 252
- Getting Technical Support 254
- Altera.com account 255
- Eighteen 256
- Getting Online Help 257
- Other Quartus II Software 259
- Documentation 259
- Other Altera Literature 260
- OTHER ALTERA LITERATURE 261
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